MOS transistors formed from a structure comprising a semiconductor layer resting on an insulating layer, itself resting on a substrate, that is, an SOI-type structure (“Semiconductor On Insulator”) are known.
FIG. 1 shows a first example of a MOS transistor formed from an SOI-type structure.
MOS transistor 1 of FIG. 1 comprises, between source and drain regions 3, a channel region 5 arranged under a gate stack 7 laterally bordered with spacers 9. Regions 3 and 5 are formed in a semiconductor layer 11. Semiconductor layer 11 rests on an insulating layer 13, itself resting on a semiconductor substrate 15, layers 11 and 13 forming an SOI-type structure. The transistor is laterally delimited and insulated by insulating walls 17 crossing semiconductor layer 11 and insulating layer 13.
In such a transistor, the thickness of semiconductor layer 11 is very small, from a few nanometers to a few tens of nanometers, which enables, in operation, to obtain a fully depleted channel region 5. However, this causes various disadvantages, particularly for the resistance of access to the source and to the drain, which increases when the thickness of layer 11 decreases.
FIG. 2 shows a second example of a MOS transistor.
MOS transistor 21 of FIG. 2, similar to MOS transistor 1, further comprises, on regions 3, epitaxial semiconductor regions 23 which contribute to increasing the thickness of the source and drain regions. Each region 23 laterally borders the corresponding gate spacer 9 along part of its height.
A disadvantage of such a transistor is that the stray capacitance between the gate stack and the source and drain regions increases.
Such MOS transistors and their manufacturing methods have various disadvantages, and the present disclosure aims at overcoming at least some of these.